Why Don't I See a CPURST Signal When I Boot an E5 Device from External Flash or Serial PROM?

Some E5 applications, where the CPURST sideband signal connects to logic in the CSL matrix, sometimes exhibit unexpected behavior at power-up or when the RST- signal is de-asserted.

In the E5 family, the CPURST sideband signal is asserted whenever the embedded 8051 microcontroller (MCU) is reset. The 8051 MCU is reset under the following conditions.

· Upon power-up.

· When the RST- pin is asserted.

· When the Watchdog Timer expires, if so configured.

· When the application reset sideband signal, RSTC, is asserted.

· Under JTAG control by either a FORCE_BRST or J_RESET JTAG command.

The problem may appear intermittent. Some applications may only work correctly when downloaded via JTAG and not in stand-alone applications. This situation occurs because the CSL logic function always sees the CPURST sideband signal asserted when the application is downloaded via JTAG. At the end of the JTAG download procedure, FastChip DeviceLink (FDL) software issues a J_RESET JTAG command, which resets the 8051. This is true whether downloading directly to internal SRAM or programming external Flash. When the 8051 is reset, the CPURST sideband signal is asserted.

However, when booting directly from byte-wide Flash or serial PROM, the E5-based system may behave differently. This happens because the CPURST signal happens before the CSL logic is programmed.

The following details the events that occur during initialization from an external Flash or serial PROM.

· The E5 device is powered up or the RST- pin is released, allowing the E5 to begin its initialization process. In either case, the embedded CPU is either reset by the power-on reset (POR) circuit or held in reset by the RST- pin and the CPURST sideband signal is asserted High. Nothing has yet been programmed into the E5.

· The embedded 8051 microcontroller begins executing the primary initialization program stored in the internal boot ROM within the E5 device. The main purpose of the primary initialization program is to determine the initialization mode and to locate the secondary initialization program, stored in either an external byte-wide static memory (Flash, EPROM, etc.) or in an external serial PROM.

· Upon locating a valid initialization header in external memory, the 8051 jumps to the external memory and begins executing the secondary initialization program stored there. The secondary initialization program configures the DMA controller to copy the CSL logic image from external memory into the configuration memory within the E5 device. The secondary initialization program then sets up the E5's data and code mappers.

· One of the last steps performed by the secondary initialization program is to enable the code mappers and to begin executing the user's application program, stored at location 0x0000. To accomplish this task, the secondary initialization program jumps to an instruction stored at the very end of the internal boot ROM, at physical address 0x2000_FFFF. The instruction enables the code mappers to point to the user's application program and the 8051's program counter rolls over to address 0x0000.

The 8051 then begins executing the user's application program. Note that the CPURST signal was only asserted once, before the 8051 began executing its initialization program. There was no logic design loaded into the CSL matrix at that time.

There are a few potential work-arounds should an application require that the CPURST signal be asserted and recognized by the CSL matrix. One option is to create a Command Register within the CSL matrix that drives the RSTC sideband signal under software control. The RSTC signal resets the 8051 CPU. Whenever the CPU is reset, the CPURST signal is asserted High. The control software should also set a semaphore flag in the on-chip XDATA RAM, which is not reset along with the CPU. Consequently, the application program can determine that the CPU has already been reset once.

There is also a hardware approach described in the following solution. Using a single selector and a flip-flop, the CSL can determine when the 8051 is completing its secondary initialization program and switching to the user's application.